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preliminary NJU3427 -1- ver.2005-10-24 36 outputs vfd controller/driver general description the NJU3427 is a 36-output vfd (vacuum fluorescent display) controller/driver. the NJU3427 consists of high-voltage driving circuit, timing/ segment driver select circuit, display data ram (ddram), address counter, instruction register, reset circuit serial interface and oscillator. the direct control from the mpu and high voltage drivers make the NJU3427 well suited for various vfd displays features display capability from 20-seg x 16-timing to 28-seg x 4-timing dr0 pin (i so1 ) 20ma(v dd =5v) dr1~dr35 pins (i so2 ) 10ma(v dd =5v) segment and timing driver configure 4 patterns high vfd driving voltage |v dd -v fdp | 40v programmable display duty ratio 1/4, 1/8, 1/12 or 1/16 programmable timing signal duty ratio 2/16, 4/16, 6/16, 8/16, 10/16, 12/16, 14/16, 15/16 display on/off display data ram 47 x 8 bits cr oscillator external cr and capable of clock input from outside serial data transfer clock frequency: 2mhz max. logic power supply 3.0v / 5.0v c-mos package qfp52 block diagram package NJU3427f xtb si sck rstb csb dr35 segment data latch osc timing counter v dd v ss v fdp serial buffer timing decoder dr0 reset instruction decoder duty counter display ram hi g h volta g e drivers xt address counter timin g /se g ment select
NJU3427 preliminary - 2 - ver.2005-10-24 pin configuration pin description no. symbol function 42 v dd logic power supply 3.0v / 5.0v 44 v ss gnd v ss =0v 40 v fdp power supply for vfd driving 2 ~ 13, 15 ~ 38 dr0~ dr35 driving signal output the configure of the segment and timing drivers is determined by the instruction, refer to (2) instruction register. 52 rstb reset if rstb=?l", reset occurs, but data on ddram not changing. 51 csb chip select if csb=?l", data transmission is enabled. 48 sck serial clock 49 si serial data input (8-bit/one word) 45, 46 xt, xtb connecting external capacitor and resistor, or input clock via this pin if using external clock, input clock signal via xt and keep xtb open. 1, 14, 39, 41, 43, 47, 50 nc no connect usually open. dr7 dr9 dr11 dr10 dr8 xt xtb nc sck si nc csb rstb 52 nc dr6 dr5 dr4 dr3 dr2 dr1 dr0 3 2 1 6 5 4 9 8 7 11 10 12 1 3 51 50 49 48 47 46 45 44 43 42 41 40 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 NJU3427f nc dr12 dr13 dr14 dr15 dr16 dr17 dr18 dr19 dr20 dr21 dr22 dr23 dr24 dr25 dr26 dr27 dr28 dr29 dr30 dr31 dr32 dr33 dr34 dr35 nc v ss v fdp v dd nc nc
preliminary NJU3427 -3- ver.2005-10-24 function description (1) address counter the address counter specifies the ram address, and the display data from cpu is written to the specified address. if the upper 2 bits (b7, b6) of the 1 st word are ?0,0?, the rest 6 bits (b5~b0) will be interpreted as ram address. the 2 nd word will be interpreted as display data and saved on the ram which address is specified by the b5~b0 of the 1 st data. once the ram address is determined by the 1 st data, the address counter will automatically increase (+1) for every following word. so there is no need to specify the address for every word for a consecutive data transfer. during display data writing, even there is unused or not-existing ram area, be sure to input 8-bit serial data. the data allocated to the above mentioned area is invalid. the ram address range varies with programmable duty ratios. for 1/4 duty, the address range is from?00h~0fh?. for 1/8 duty, the range is from ?00h~1fh?. for 1/12 duty, the range is from ?00h~23h?. for 1/16 duty, the range is from ?00h~2fh?. when automatically increased address excess the address range and display data is still transferred from cpu, the address counter will return to ?00h? and count up again. address data b7 0 address flag b6 0 b5 ad5 b4 ad4 b3 ad3 b2 ad2 b1 ad1 b0 ad0 ram address
NJU3427 preliminary - 4 - ver.2005-10-24 ddram map1 1/16 duty (t=16, s=20) 1/12 duty (t=12, s=24) not-using ram area not-existing ram area
preliminary NJU3427 -5- ver.2005-10-24 ram map 2 1/8 duty (t=8, s=28) 1/4 duty (t=4, s=28) not-using ram area not-existing ram area
NJU3427 preliminary - 6 - ver.2005-10-24 (2) instruction register 1 the instruction register 1 is used for setting duty ratio and driver (dr) pins configure. if b7 of the 1 st word is ?1?, the rest 4 bits (b5, b4, b1, b0) is interpreted as instruction 1. the value on register is initialized to the default by reset signal. but, during power on, the value of register 1 is unspecified, it is necessary to set value in register 1. the contents of the ?instruction register 1? is initially set up by reset signal, as shown below. because the NJU3427 is unstable during power on, reset shall be executed. instruction register 1 default duty ratio 1/16 dr pins pattern 1 dy1 dy0 duty ratio 0 0 1/16 0 1 1/12 1 0 1/8 1 1 1/4 note): for segment and timing pins configure, please refer to ?the relationship between duty ratio and segment/timing pins?. when select 1/4 and 1/8 duty, configures of segment and timing pins are the same. dr1 dr0 dr configure 0 0 pattern 1 0 1 pattern 2 1 0 pattern 3 1 1 pattern 4 note): for segment and timing pins configure, please refer to ?the relationship between duty ratio and segment/timing pins?. b7 1 instruction fla g b6 * b5 dy1 b4 dy0 b3 * b2 * b1 dr1 b0 dr0 duty ratio dr pins configure
preliminary NJU3427 -7- ver.2005-10-24 the relationship between duty ratio and segment (s)/timing (t) pins configure ? pattern 1 ? pattern 2 ? pattern 3 ? pattern 4 interface 1/16 duty nc t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 nc s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 t15 t14 t13 t12 nc interface 1/12 duty nc t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 nc s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 nc interface 1/8 or 1/4 nc t0 t1 t2 t3 t4 t5 t6 t7 s27 s26 s25 s24 nc s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 nc 1/16 duty nc t0 t1 s19 s18 t2 t3 s17 s16 s15 t4 t5 s14 nc s0 s1 s2 t15 t14 s3 s4 t13 t12 s5 s6 s7 t11 t10 s8 s9 t9 t8 s10 s11 s12 t7 t6 s13 nc 1/12 duty nc t0 s23 s22 t1 s21 s20 t2 s19 s18 t3 s17 s 1 6 nc s0 s1 t11 s2 s3 t10 s4 s5 t9 s6 s7 t8 s8 s9 t7 s10 s11 t6 s12 s13 t5 s14 s15 t4 nc 1/8 or 1/4 nc t0 s27 s26 s25 s24 t1 s23 s22 s21 s20 t2 s 1 9 nc t7 s0 s1 s2 s3 t6 s4 s5 s6 s7 t5 s 8 s9 s10 s11 t4 s12 s13 s14 s15 t3 s16 s17 s18 nc interface interface interface interface interface interface 1/16 duty nc t0 t1 t2 t3 t4 t5 s19 s18 t6 s17 s16 t7 nc t15 s0 s1 t14 s2 s3 t13 s4 s5 t12 s6 s 7 t11 s8 s9 t10 s10 s11 t9 s12 s13 t8 s14 s15 nc 1/12 duty nc t0 s23 s22 s21 s20 t1 s19 s18 t2 s17 s16 t 3 nc t11 s0 s1 t10 s2 s3 t9 s4 s5 t8 s6 s7 t7 s8 s9 t6 s10 s11 t5 s12 s13 t4 s14 s15 nc 1/8 or 1/4 nc t0 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s 1 7 nc t7 s0 s1 t6 s2 s3 t5 s4 s5 t4 s6 s 7 t3 s8 s9 t2 s10 s11 t1 s12 s13 s14 s15 s16 nc interface interface interface 1/16 duty nc t0 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s 9 nc t15 s0 s1 s2 s3 s4 s5 s6 s7 s8 t14 t13 t12 t11 t10 t9 t8 t7 t6 t5 t4 t3 t2 t1 nc 1/12 duty nc t0 s23 s22 s21 s20 s19 s18 s17 s16 s15 s14 s 1 3 nc t11 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 t10 t9 t8 t7 t6 t5 t4 t3 t2 t1 nc 1/8 or 1/4 nc t0 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s 1 7 nc t7 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 t6 t5 t4 t3 t2 t1 nc
NJU3427 preliminary - 8 - ver.2005-10-24 (3) instruction register 2 the instruction register 2 is used for setting timing signal duty ratio and controlling display on/off. if b7 and b6 of the 1 st word are ?0, 1?, the rest 4 bits (b4~b1) is interpreted as instruction 2. when power on or reset signal input, the register 2 is initialized as below: because the NJU3427 is unstable during power on, reset shall be executed. instruction register 2 default timing duty ratio 2/16 display on/off off dt2 dt1 dt0 timing duty ratio 0 0 0 2/16 0 0 1 4/16 0 1 0 6/16 0 1 1 8/16 1 0 0 10/16 1 0 1 12/16 1 1 0 14/16 1 1 1 15/16 note): for the output waveform, refer to ? timing signal duty ratio ?. dsp display control 0 off 1 on note): during display off, there is no signal from timing pins and segment pins. timing signal duty ratio b7 0 instruction flag b6 1 b5 * b4 dt2 b3 dt1 b2 dt0 b1 dsp b0 * dis p la y on/off
preliminary NJU3427 -9- ver.2005-10-24 timing signal and duty ratio frame time (duty counter value) timing driver (t 0 ~t 15 ) segment driver 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 dt1 dt0 dt2 0 0 0 2/16 0 1 0 4/16 1 0 0 6/16 1 1 0 8/16 0 0 1 10/16 0 1 1 12/16 1 0 1 14/16 1 1 1 15/16
NJU3427 preliminary - 10 - ver.2005-10-24 display timing charter ? duty ratio 1/16 external clock frequency 800khz~2.5mhz f cl minimum blinking time 40 s~12.8 s t bk =(1/f cl ) x 16 x 2 (timing signal duty ratio = 15/16) 1-character display time 640 s ~204.8 s t dg =t bk x 16 frame time 10.24ms~3.2768ms t sp =t dg x 16 ? duty ratio 1/12 external clock frequency 800khz~2.5mhz f cl minimum blinking time 55 s~17.6 s t bk =(1/f cl ) x 22 x 2 (timing signal duty ratio = 15/16) 1-character display time 880 s ~281.6 s t dg =t bk x 16 frame time 10.56ms~3.3792ms t sp =t dg x 12 t bk t dg ? ? ? t sp f cl t0 t1 t2 t15 s0~s19 ? ? ? t3 f cl t bk t dg ? ? ? t sp f cl t0 t1 t2 t11 s0~s23 ? ? ? t3 f cl
preliminary NJU3427 -11- ver.2005-10-24 ? duty ratio 1/8 external clock frequency 800khz~2.5mhz (f cl ) minimum blinking time 80 s~25.6 s t bk =(1/f cl ) x 32 x 2 (timing signal duty ratio = 15/16) 1-character display time 1.28ms~409.6 s t dg =t bk x 10 frame time 10.24ms~3.2768ms t sp =t dg x 8 ? duty ratio 1/4 (t4~t7 output pins) external clock frequency 800khz~2.5mhz (f cl ) minimum blanking time 160 s~51.2 s t bk =(1/f cl ) x 64 x 2 (timing signal duty ratio = 15/16) 1-character display time 2.56ms~819.2 s t dg =t bk x 16 frame time 10.24ms~3.2768ms t sp =t dg x 4 t bk t dg ? ? ? t sp f cl t0 t1 t2 t7 s0~s27 ? ? ? t3 f cl t bk t dg ? ? ? t sp f cl t0 t1 t2 t7 s0~s27 ? ? ? t3 f cl
NJU3427 preliminary - 12 - ver.2005-10-24 (4) serial interface 8-bit per word serial data is transferred from cpu to NJU3427 with synchronous clock signal (sck). at the every rising edge of the sck, data is taken in, and at the rising edge of csb, the data of words are latched. if the 1 st data is address data when csb becoming ?l?, without changing csb, the following data will be interpreted as display data. if the 1 st data is instruction, without changing csb signal, all the following data is invalid. serial data transmission serial data transmission format ? serial data 1 st word address data b7 b6 b5 b4 b3 b2 b1 b0 0 0 ad5 ad4 ad3 ad2 ad1 ad0 instruction 1 b7 b6 b5 b4 b3 b2 b1 b0 1 * dy1 dy0 * * dr1 dr0 *:don?t care instruction 2 b7 b6 b5 b4 b3 b2 b1 b0 0 1 * dt2 dt1 dt0 dsp * *:don?t care from the 2 nd word if the 1 st word is address data display data if the 1 st word is instruction data invalid data sck si d0 d1 d2 d3 d4 d5 d6 d7 sck 1 s t word 2 n d word n th word csb si
preliminary NJU3427 -13- ver.2005-10-24 (5) reset circuit if rstb="l", reset circuit functions, and the following default is set up. because the NJU3427 is unstable during power on, reset shall be executed. address data (ad0, ad1, ad2, ad3, ad4, ad5): (0, 0, 0, 0, 0, 0) instruction register 1 duty ratio 1/16 dr pins configure pattern 1 instruction register 2 timing signal duty ratio 2/16 display on/off off
NJU3427 preliminary - 14 - ver.2005-10-24 absolute maximum ratings parameter symbol rating unit conditions power supply v dd -0.3~+7.0 v input voltage v in -0.3~v dd +0.3 v vfd driving voltage v fdp v dd -45~v dd +0.3 v v dd as reference voltage h level output current 1 i oh1 -35 ma dr 0 output, signal pin h level output current 2 i oh2 -15 ma dr 1 ~ dr 35 output, signal pin l level output current i ol 20 ma operating temperature topr -40 ~ 85 c storage temperature tstg -55 ~ 125 c power dissipation pd 900 mw glass epoxy board (76.2 x114.3x1.6mm) note 1): the ic must be used within the absolute maximum ratings, otherwise, an electrical or physical stress may cause a permanent damage to it. note 2): de-coupling capacitors should be placed between v dd -v ss and v fdp -v ss. note 3): the condition of v dd > v ss v fdp and v ss =0 must be maintained.
preliminary NJU3427 -15- ver.2005-10-24 electrical characteristics dc characteristics 1 (v dd =5.0v, v ss =0v, ta=-40 ~ 85 c) parameter symbol conditions min typ max unit power supply (1) v dd v dd pin 4.5 - 5.5 v power supply (2) v fdp v fdp pin and v dd as reference -40 - v ss v h level input voltage v ih 0.8v dd - - l level input voltage v il xt, rstb, csb, sck, si pins - - 0.2v dd v input off-leak current i iz csb, sck, si pins v dd =5.5v, v i =0 or 5.5v - - 1 a dr 0 pin -11.5 -20 - ma display current i oh dr 1 ~ dr 35 pin v dd =4.5v,v fdp =v dd -40 v, v oh =v dd -2.25v -5.5 -10 - ma pull-up resistance r ur rstb pin, ta=25 c, v i =v ss 100 - 300 k ? pull-down resistance r dst dr 0 ~ dr 35 pins, ta=25 c v i =v dd , v fdp =v dd -40v 75 - 195 k ? logic circuit power supply i ss v ss pin cr oscillation (r=6.8k ? , c=100pf), all segment/timing pins open, rstb open all segment/timing pins output display off signal. - 0.6 0.8 ma operation current i fdp v fdp pin, v fdp =v dd -40v, cr oscillation (r=6.8k ? , c=100pf), a ll driving pins output display on signal - 12 16.5 ma cr oscillation frequency f cr ta=25 c r=6.8k ? , c=100pf 1.05 1.13 1.21 mhz ? ac characteristics 1 (v dd =5.0v, v ss =0v, ta=-40 ~ 85 c) parameter symbol conditions min typ max unit external clock frequency f cl fig 1 0.8 - 2.5 mh z width of external clock pulse t clh , t cll fig 1 200 ns data setup time t sis fig2 35 ns data hold time t sih fig2 35 ns clock frequency f sck fig3 2.0 mh z clock pulse width t sckh , t sckl fig3 200 ns external clock rising time, falling time t clh , t cll fig2 250 ns clock interval time t sci fig3 10 s reset pulse width t rstb fig4 10 s
NJU3427 preliminary - 16 - ver.2005-10-24 ? dc characteristics 2 (v dd =3.0v, v ss =0v, ta=-40 ~ 85 c) parameter symbol conditions min typ max unit power supply (1) v dd v dd pin 2.7 - 3.6 v power supply (2) v fdp v fdp pin and v dd as reference -40 - v ss v h level input voltage v ih 0.8v dd - - l level input voltage v il xt, rstb, csb, sck, si pins - - 0.2v dd v input off-leak current i iz csb, sck, si pins v dd =3.6v, v i =0 or 3.6v - - 1 a dr 0 pin -5.0 -9.0 - ma display current i oh dr 1 ~ dr 35 pin v dd =2.7v,v fdp =v dd -40 v, v oh =v dd -1.35v -2.5 -4.0 - ma pull-up resistance r ur rstb pin, ta=25 c, v i =v ss 100 - 300 k ? pull-down resistance r dst dr 0 ~ dr 35 pins, ta=25 c v i =v dd , v fdp =v dd -40v 75 - 195 k ? logic circuit power supply i ss v ss pin cr oscillation (r=4.7k ? , c=100pf), all segment/timing pins open, rstb open all segment/timing pins output display off signal. - 0.25 0.35 ma operation current i fdp v fdp pin, v fdp =v dd -40v, cr oscillation (r=4.7k ? , c=100pf), a ll driving pins output display on signal - 12 16.5 ma cr oscillation frequency f cr ta=25 c r=4.7k ? , c=100pf 1.05 1.13 1.21 mhz ? ac characteristics 2 (v dd =3.0v, v ss =0v, ta=-40 ~ 85 c) parameter symbol conditions min typ max unit external clock frequency f cl fig 1 0.8 - 2.5 mh z width of external clock pulse t clh , t cll fig 1 200 ns data setup time t sis fig2 35 ns data hold time t sih fig2 35 ns clock frequency f sck fig3 2.0 mh z clock pulse width t sckh , t sckl fig3 200 ns external clock rising time, falling time t clh , t cll fig2 250 ns clock interval time t sci fig3 10 s reset pulse width t rstb fig4 10 s
preliminary NJU3427 -17- ver.2005-10-24 fig1 fig2 fig3 fig4 t rstb rstb v il v il xt f cl v ih v ih v ih v il v il t clh t cll v ih v ih v il v il t sis t sih sck si t clh t cll v ih v ih v il v il t sckh t sckl t sci f sck csb sck t sci t sci v il v il v il v ih v ih v ih v il v ih v il rstb
NJU3427 preliminary - 18 - ver.2005-10-24 application circuit (cr oscillation) * pay careful attention to reduce the noise from power supply and interface pins. n.c. csb sck si n.c. NJU3427f n.c. cpu vfd v fdp dr 0 c0 r dr 1 dr 2 dr 3 dr 4 dr 5 dr 6 dr 7 dr 8 dr 9 dr 10 dr 11 dr 12 dr 13 dr 14 dr 15 dr 16 dr 17 dr 18 dr 19 dr 20 dr 21 dr 22 dr 23 n.c. dr 35 dr 34 dr 33 dr 32 dr 31 dr 30 dr 29 dr 28 dr 27 dr 26 dr 25 dr 24 rstb n.c. xtb xt v ss n.c v dd n.c. v fdp v dd c0 c
preliminary NJU3427 -19- ver.2005-10-24 qfp52 package [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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